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MP8720 26v,10a, high efficiency , fast transient, synchronous, buck converter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 1 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the future of analog ic technology description the MP8720 provides a complete power supply with the highest power density for system powers, such as ddr memory and usb type-c. the MP8720 integrates a high-frequency, synchronous, rectified, step-down, switch-mode converter (v out ) with an adjustable current limit (clm). the MP8720 operates at high efficiency over a wide output current load range based on mps?s proprietary switching loss reduction technology and internal low r ds(on) power mosfets. adaptive constant-on-time (cot) control mode provides fast transient response and eases loop stabilization. the dc auto-tune loop provides good load and line regulation. by setting clm, the current limit can be adjusted from 8.5a to 16.5a for different mode applications. full protection features include over-current limit (ocl), over-voltage protection (ovp), under-voltage protection (uvp), and thermal shutdown. the MP8720 requires a minimal number of external components and is available in a qfn- 16 (3mmx3mm) package. features ? wide 4.5v to 26v operating input range ? compatible for usb type-c ? 10a continous output current ? adjustable current limit from 8.5a to 16.5a ? fixed 700khz switching frequency ? adaptive cot for fast transient ? dc auto-tune loop ? stable with poscap and ceramic output capacitors ? internal soft start (ss) ? selectable pulse skip or forced ccm ? output adjustable from 0.8v to 5.5v ? ocl, ovp, uvp, and thermal shutdown ? latch-off reset via en or power cycle ? available in a qfn-16 (3mmx3mm) package applications ? televisions ? networking systems ? distributed power system ? set-top-box a ll mps parts are lead-free, halogen-free, and adhere to the rohs directive. for mps green status , please visit the mps website unde r quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 2 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ordering information part number* package top marking MP8720gq qfn-16 (3mmx3mm) see below * for tape & reel, add suffix ?z (e.g. MP8720gq?z) top marking bct: product code of MP8720gq; y: year code; lll: lot number; package reference top view qfn-16 (3mmx3mm)
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 3 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. absolute maxi mum ratings (1) supply voltage (vin) .................................... 26v v sw (dc) ................................. -1v to vin + 0.3v v sw (25ns) .......................... -3.6v to vin + 4v (2) v bst ................................................... v sw + 4.5v all other pins ................................ -0.3v to +4.5v continuous power dissipation (t a = +25c) (3) qfn-16 (3mmx3mm) ................................. 2.3w junction temperature ................................ 150c lead temperature ..................................... 260c storage temperature ................ -65c to +150c recommended operating conditions (4) supply voltage (vin) ........................ 4.5v to 24v supply voltage (v cc ) ..................... 3.15v to 3.5v output voltage (v out ) ...................... 0.8v to 5.5v operating junction temp. (t j ). .. -40c to +125c thermal resistance (5) ja jc qfn-16 (3mmx3mm) ............. 55 ....... 13 ... c/w notes: 1) exceeding these ratings may damage the device. 2) measured by using differential oscilloscope probe. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation produces an excessive die temper ature, causing the regulato r to go into thermal shutdown. internal thermal shutdown circuitry protects the dev ice from permanent damage. 4) the device is not guaranteed to function outside of its operating conditions. 5) measured on jesd51-7, 4-layer pcb.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 4 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics vin = 12v, 3v3 = 3.3v, t j = 25c, r mode = 0 ? , unless otherwise noted. parameters symbol condition min typ max units supply current 3v3 supply current i 3v3 v en = 3v, v fb = 0.65v, no load 140 230 a 3v3 shutdown current i 3v3 sdn v en = 0v, no load 1 a mosfet high-side switch on resistance hs rds-on t j = 25c 19 m ? low-side switch on resistance ls rds-on t j = 25c 7 m ? switch leakage sw lkg v en = 0v, v sw = 0v 0 1 a current limit low-side valley current limit i limit clm = 0 ? 8.5 a clm = 90k ? 9 10 11 a clm = 150k ? 13 a clm = float 16.5 a switching frequency and minimum off time switching frequency fs 700 khz constant on timer t on vin = 5v, v out = 1.8v 430 515 600 ns minimum on time ( 6 ) t on min 70 ns minimum off time ( 6 ) t off min 240 ns protection ovp threshold v ovp 125 130 135 %v ref uvp-1 threshold v uvp-1 70 75 80 %v ref uvp-1 foldback timer ( 6 ) t uvp-1 30 s uvp-2 threshold v uvp-2 45 50 55 %v ref reference and soft start, soft stop reference voltage v ref 594 600 606 mv feedback current i fb v fb = 0.62v 10 50 na soft-start time t sstart en to pg up 1.8 2.2 2.6 ms mode mode source current i mode 9 10 11.4 a enable and uvlo en rising threshold v en th 1.12 1.22 1.32 v en hysteresis v en-hys 125 mv enable input current i en v en = 2v 5 a v en = 0v 1 vcc under-voltage lockout threshold rising vcc vth 2.9 3.0 3.1 v vcc under-voltage lockout threshold hysteresis vcc hys 220 mv vin under-voltage lockout threshold rising vin vth 4.2 4.4 v vin under-voltage lockout threshold hysteresis vin hys 360 mv
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 5 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics (continued) vin = 12v, 3v3 = 3.3v, t j = 25c, r mode = 0 ? , unless otherwise noted. parameters symbol condition min typ max units power good pg when fb rising (good) pg _rising(good) v fb rising, percentage of v fb 95 % pg when fb falling (fault) pg _falling(fault) v fb falling, percentage of v fb 90 pg when fb rising (fault) pg _rising(fault) v fb rising, percentage of v fb 115 pg when fb falling (good) pg _falling(good) v fb falling, percentage of v fb 105 pg low to high delay pg td 3 s en low to pg low delay pg td en low 1 s power good sink current capability v pg sink 4ma 0.4 v thermal protection thermal shutdown ( 6 ) t sd 150 c thermal shutdown hysteresis t sd hys 25 c note: 6) guaranteed by design.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 6 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pin functions pin # name description 1 vin supply voltage. vin supplies power for the internal mosfet and regulator. the MP8720 operates from a +4.5v to +26v input rail. an input capacitor is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 2, 4, 5, 6, 7 pgnd power ground. use wide pcb traces and multiple vias to make the connection. 3 3v3 external 3v3 vcc input for control and driver. place a 1f decoupling capacitor close to 3v3 and pgnd. it is recommended to form an r-c filter. 8, 16 nc no connection. nc can either be connected to vi n, sw, or gnd for easy layout. 9 sw switch output. connect sw to the inductor and bootstrap capacitor. sw is connected to vin when the hs-fet is on. sw is conne cted to pgnd when the ls-fet is on. use wide and short pcb traces to make the conn ection. sw is noisy, so keep sensitive traces away from sw. 10 bst bootstrap. a capacitor connected between sw and bst is required to form a floating supply across the high-side switch driver. 11 clm current limit adjust. there are four settings for the current, which can be set by connecting clm to gnd with different kinds of resistors. 12 pg power good output. pg is an open-drain signal. pg is high if the output voltage is within a proper range. 13 fb feedback. an external resistor divider from the output to gnd tapped to fb sets the output voltage. place the resistor divider as close to fb as possible. avoid vias on the fb traces. 14 mode mode. select mode for different output ranges and to select dcm or ccm. 15 en enable. when en = 1, the regulator turns on; when en = 0, the regulator turns off.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 7 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics vin = 12v, v out = 5v, l = 1.5h, dcr = 10m ? , f sw = 700khz, dcm, clm = 16a, t j = +25c, unless otherwise noted. 50 60 70 80 90 100 0.01 0.1 1 10 efficiency(%) load ? current(a) efficiency v out =1.2v, ? f sw =700khz, ? l=0.68h, ? dcr=3.1m ? , r bst =0 ? ,c out =3x22f, ? dcm ? mode vin=5v vin=8.4v vin=12v vin=19v 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 0.01 0.1 1 10 power ? loss(mw ) load ? current(a) power ? loss v out =1.2v, ? f sw =700khz, ? l=0.68h, ? dcr=3.1m ? , r bst =0 ? ,c out =3x22f, ? dcm ? mode vin=5v vin=8.4v vin=12v vin=19v \ 1 \ 0.8 \ 0.6 \ 0.4 \ 0.2 0 0.2 0.4 0.6 0.8 1 0.01 0.1 1 10 load ? regulation ? (%) load ? current(a) load ? regulation ? vs. ? load ? current v out =1.2v, ? f sw =700khz, ? l=0.68h, ? dcr=3.1m ? , r bst =0 ? ,c out =3x22f, ? dcm ? mode vin=5v vin=8.4v vin=12v vin=19v 50 60 70 80 90 100 0.01 0.1 1 10 efficiency(%) load ? current(a) efficiency ? v out =5v, ? f sw =700khz, ? l=1.5h, ? dcr=10m ? , r bst =0 ? ,c out =5x22f, ? dcm ? mode vin=5.5v vin=8.4v vin=12v vin=19v 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0.01 0.1 1 10 power ? loss(mw) load ? current(a) power ? loss ? v out =5v, ? f sw =700khz, ? l=1.5h, ? dcr=10m ? , r bst =0 ? ,c out =5x22f, ? dcm ? mode vin=5.5v vin=8.4v vin=12v vin=19v \ 2 \ 1.5 \ 1 \ 0.5 0 0.5 1 1.5 2 0.01 0.1 1 10 load ? regulation ? (%) load ? current(a) load ? regulation v out =5v, ? f sw =700khz, ? l=1.5h, ? 744323150, ? c out =3x47f, ? r9=100k ? , r10=11.3k ? ,r bst =0 ? , ? c4=220pf, ? r4=360k ? vin=6v vin=8.4v vin=12v vin=19v
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 8 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) vin = 12v, v out = 5v, l = 1.5h, dcr = 10m ? , f sw = 700khz, dcm, clm = 16a, t j = +25c, unless otherwise noted. \ 2 \ 1.5 \ 1 \ 0.5 0 0.5 1 1.5 2 6 8 10 12 14 16 18 20 22 24 line ? regulation ? (%) load ? current(a) line ? regulation v out =5v, ? f sw =700khz, ? l=1.5h, ? 744323150, ? c out =3x47f, ? r9=100k ? , r10=11.3k ? ,r bst =0 ? , ? c4=220pf, ? r4=360k ? iout=0a iout=0.1a iout=1a iout=10a 0 10 20 30 40 50 60 70 012345678910 temprature ? rise ? ( o c) output ? current(a) temperature ? rise ? with ? load ? current v out =5v, ? f sw =700khz, ? l=1.5h, ? dcr=4.3m ? , r bst =0 ? ,c out =4x22f, ? dcm ? mode vin=19v 0 100 200 300 400 500 600 700 800 900 0246810 frequency ? (khz) load ? current(a) frequency ? vs. ? load ? current v out =5v, ? f sw =700khz, ? l=1.5h, ? dcm ? mode vin=6v vin=8.4v vin=12v vin=19v 0 100 200 300 400 500 600 700 800 900 6 8 10 12 14 16 18 20 22 24 frequency (khz) input ? voltage ? (v) frequency ? vs. ? input ? voltage v out =5v, ? f sw =700khz, ? l=1.5h, ? dcm ? mode iout=2a iout=10a 6 8 10 12 14 16 18 \ 40 \ 200 20406080100120 current limit (a) temperature ( o c) current limit vs. temperature clm=8.5a clm=10a clm=13a clm=16.5a
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 9 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) vin = 12v, v out = 5v, l = 1.5h, dcr = 10m ? , f sw = 700khz, dcm, clm = 16a, t j = +25c, unless otherwise noted. input/output voltage ripple i out = 0a, dcm input/output voltage ripple i out = 0a, ccm ch1: v out /ac 50mv/div. ch2: v in /ac 100mv/div. ch3: v sw 10v/div. ch4: i l 2a/div. ch1: v out /ac 50mv/div. ch2: v in /ac 200mv/div. ch3: v sw 20v/div. ch4: i l 10a/div. 4ms/div. 2s/div. input/output voltage ripple i out = 10a, dcm input/output voltage ripple i out = 10a, ccm ch1: v out /ac 50mv/div. ch2: v in /ac 1v/div. ch3: v sw 20v/div. ch4: i l 10a/div. ch1: v out /ac 50mv/div. ch2: v in /ac 500mv/div. ch3: v sw 20v/div. ch4: i l 10a/div. 2s/div. 2s/div. power good through en start-up i out = 0a, dcm power good through en start-up i out = 10a, dcm ch1: v out 5v/div. ch2: v en 5v/div. ch3: v sw 20v/div. ch4: v pg 5v/div. ch1: v out 5v/div. ch2: v en 5v/div. ch3: v sw 20v/div. ch4: v pg 5v/div. 400s/div. 400s/div.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 10 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) vin = 12v, v out = 5v, l = 1.5h, dcr = 10m ? , f sw = 700khz, dcm, clm = 16a, t j = +25c, unless otherwise noted. power good through en shutdown i out = 0a, dcm power good through en shutdown i out = 10a, dcm ch1: v out 5v/div. ch2: v en 5v/div. ch3: v sw 10v/div. ch4: v pg 5v/div. ch1: v out 5v/div. ch2: v en 5v/div. ch3: v sw 10v/div. ch4: v pg 5v/div. 2ms/div. 100s/div. transient vin = 19v, l = 1.5 h, c out = 6 x 22 f, dcm, i out = 1a - 9a @ 2.5a/ s transient vin = 19v, l = 1.5 h, c out = 6 x 22 f , ccm, i out = 1a - 9a @ 2.5a/ s ch1: v out /ac 200mv/div. ch4: i l 5a/div. ch1: v out /ac 200mv/div. ch4: i l 5a/div. 400s/div. 400s/div. short-circuit protection through en up set clm = 8.5a, vin = 19v short-circuit protection through en up set clm = 10a, vin = 19v ch1: v out 500mv/div. ch2: v en 5v/div. ch3: v sw 20v/div. ch4: i l 10a/div. ch1: v out 500mv/div. ch2: v en 5v/div. ch3: v sw 20v/div. ch4: i l 10a/div. 1ms/div. 1ms/div.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 11 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) vin = 12v, v out = 5v, l = 1.5h, dcr = 10m ? , f sw = 700khz, dcm, clm = 16a, t j = +25c, unless otherwise noted. short-circuit protection through en up set clm = 13a, vin = 19v short-circuit protection through en up set clm = 16.5a, vin = 19v ch1: v out 500mv/div. ch2: v en 5v/div. ch3: v sw 20v/div. ch4: i l 10a/div. ch1: v out 500mv/div. ch2: v en 5v/div. ch3: v sw 20v/div. ch4: i l 10a/div. 1ms/div. 1ms/div. thermal shutdown vin = 19v, i out = 10a thermal recovery vin = 19v, i out = 10a ch1: v out 5v/div. ch2: v pg 5v/div. ch3: v sw 20v/div. ch4: i l 10a/div. ch1: v out 5v/div. ch2: v pg 5v/div. ch3: v sw 20v/div. ch4: i l 10a/div. 20s/div. 1ms/div. en pre-bias start-up vin = 19v, i out = 10a ovp circuit protection vin = 19v, i out = 10a, force v out = 6.8v ch1: v out 2v/div. ch2: v en 2v/div. ch3: v sw 10v/div. ch4: i l 5a/div. ch1: v out 5v/div. ch2: v in 20v/div. ch3: v sw 5v/div. ch4: i l 5a/div. 400s/div. 10ms/div.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 12 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. block diagram control logic on time one shot fault logic soft start por & reference 130% vref ovp oc limit pok min off time fb 95% vref vddq sw bstreg vin bst sw pgnd pg 3v3 output discharge v in dc error correction + + fb ref vref fb agnd en clm mode 3v3 uvp-2 uvp-1 75% vref 50% vref figure 1: functional block diagram
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 13 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. r operation pulse-width modulation (pwm) operation the MP8720 is a fully integrated, synchronous, rectified, step-down, switch-mode converter with an adjustable current limit (clm). constant-on-time (cot) control provides fast transient response and eases loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ), which indicates an insufficient output voltage. the on period is determined by both the output voltage and the input voltage to make the switching frequency fairly constant over the input voltage range. after the on period elapses, the hs-fet is turned off or enters an off state. the hs-fet is turned on again when v fb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize conduction loss. a dead short occurs between the input and gnd if both the hs-fet and the ls-fet are turned on at the same time. this is called shoot-through. to prevent shoot-through, a dead time (dt) is generated internally between the hs-fet off and the ls-fet on period or the ls-fet off and the hs-fet on period. internal compensation is applied for cot control for stable operation, even when ceramic capacitors are used as output capacitors. this internal compensation improves the jitter performance without affecting the line or load regulation. heavy-load operation continuous conduction mode (ccm) occurs when the output current is high and the inductor current is always above zero amps (see figure 2). when v fb is below v ref , the hs-fet is turned on for a fixed interval determined by the one-shot on timer. when the hs-fet is turned off, the ls-fet is turned on until the next period. in ccm operation, the switching frequency is fairly constant (pulse-width modulation (pwm) mode). figure 2: ccm operation light-load operation when the load decreases, the inductor current decreases as well. once the inductor current reaches zero, the MP8720 transitions from ccm to discontinuous conduction mode (dcm). dcm operation is shown in figure 3. when v fb is below v ref , the hs-fet is turned on for a fixed interval determined by the one- shot on timer. when the hs-fet is turned off, the ls-fet is turned on until the inductor current reaches zero. in dcm operation, the v fb does not reach v ref when the inductor current is approaching zero. the ls-fet driver turns into tri-state (hi-z) when the inductor current reaches zero. a current modulator takes over the control of the ls-fet and limits the inductor current to less than -1ma. therefore, the output capacitors discharge slowly to gnd through the ls-fet. as a result, the efficiency during light-load condition improves greatly. the hs-fet does not turn on as frequently during a light-load condition as it does during a heavy-load condition (skip mode). at a light-load or no-load condition, the output drops very slowly, and the MP8720 reduces the switching frequency naturally, achieving high efficiency at light load. figure 3: dcm operation
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 14 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. as the output current increases from light-load condition, the current modulator regulation time period becomes shorter. the hs-fet is turned on more frequently, making the switching frequency increases. the output current reaches the critical level when the current modulator time is zero. the critical level of the output current is determined with equation (1): in s out out in critical _ out v f l v ) v v ( i ? ? ? ? ? ? 2 (1) the MP8720 enters pwm mode once the output current exceeds the critical level. afterward, the switching frequency remains fairly constant over the output current range. jitter and fb ramp jitter occurs in both pwm and skip mode when noise in the v fb ripple propagates a delay to the hs-fet driver (see figure 4 and figure 5). jitter affects system stability, with noise immunity proportional to the steepness of v fb ?s downward slope, so the jitter in dcm is usually larger than it is in ccm. however, the v fb ripple does not affect noise immunity directly. v re f v fb hs driver v noise j itter v s l o pe1 figure 4: jitter in pwm mode v fb hs driver jitter v ref v slope2 v noise figure 5: jitter in skip mode operating without external ramp compensation the traditional cot control scheme is intrinsically unstable if the output capacitor?s esr is not large enough to act as an effective current-sense resistor. usually, ceramic capacitors cannot be used directly as output capacitors. the MP8720 has built-in internal ramp compensation to ensure that the system is stable, even without the help of the output capacitor?s esr. use the pure ceramic capacitor solution, which reduces the output ripple, total bom cost, and board area significantly. figure 6 shows a typical output circuit in pwm mode without an external ramp circuit. refer to the application information section on page 17 for design steps without external compensation. figure 6: simplified output circuit when using a large capacitor (e.g.: oscon) on the output, add a >10f ceramic capacitor in parallel to minimize the effect of esl. operating with external ramp compensation usually, the MP8720 is able to support ceramic output capacitors without an external ramp. however in some cases, the internal ramp may not be enough to stabilize the system, or there is too much jitter, which requires external ramp compensation. refer to the application information section on page 17 for design steps with external ramp compensation. mode selection the MP8720 implements mode for multiple applications for output and switching mode selection. the output and switch mode can be selected by a different resistor on mode. there are four modes that can be selected for normal application with external resistors (see table 2). it is recommended to use a 1% accuracy resistor.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 15 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. table 2: mode selection state v out dcm/ccm resistor to gnd m1 vo < 3v dcm 0 ? m2 vo < 3v ccm 90k ? m3 vo 3v ccm 150k ? m4 vo 3v dcm >230k ? or float power good (pg) the MP8720 uses a power good (pg) output to indicate whether the output voltage of the v out regulator is ready. pg is the open drain of a mosfet. it should be connected to v cc or another voltage source through a resistor (e.g.: 100k ? ). after the input voltage is applied, the mosfet is turned on, so pg is pulled to gnd before ss is ready. after v fb reaches 95% of v ref , pg is pulled high (after a delay time within 10s). when v fb drops to 90% of v ref , pg is pulled low. soft start (ss) the MP8720 employs a soft-start (ss) mechanism to ensure a smooth output during power-up. when en becomes high, the internal reference voltage ramps up gradually, and the output voltage ramps up smoothly as well. once the reference voltage reaches the target value, the soft start finishes, and the MP8720 enters steady-state operation (see figure 7). figure 7: start-up power sequence if the output is pre-biased to a certain voltage during start-up, the ic disables the switching of both the high-side and the low-side switches until the voltage on the internal reference exceeds the sensed output voltage at the fb node. output discharge the MP8720 discharges the output through an internal 100 ? resistor when the controller is turned off by a protection function (uvp, ocp, ovp, uvlo, or thermal shutdown). over-current limit (ocl) the MP8720 has cycle-by-cycle over-current limiting control. the current-limit circuit employs a valley current-sensing algorithm. the MP8720 uses the r ds(on) of the ls-fet as a current- sensing element. if the magnitude of the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle, even if fb is lower than ref (see figure 8). figure 8: valley current-limit control since the comparison is done during the ls- fet on state, the over-current trip level sets the valley level of the inductor current. the maximum load current at the over-current threshold (i oc ) can be calculated using equation (2): ? ?? inductor oc i i i _ limit 2 (2) the over-current limit (ocl) limits the inductor current and does not latch off. in an over- current condition, the current to the load exceeds the current to the output capacitor, so the output voltage tends to fall off. eventually, the current ends up crossing the under-voltage protection (uvp) threshold and latches off. fault latching can be reset by en going low or cycling the power of vin. current limit (clm) selection the MP8720 implements an adjustable valley clm by connecting clm to gnd with different resistor values (see table 3).
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 16 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. table 3: clm selection state clm resistor to gnd m1 8.5a 0 ? m2 10a 90k ? m3 13a 150k ? m4 16.5a >230k ? or float over/under-voltage protection (ovp, uvp) the MP8720 monitors a resistor divided feedback voltage to detect over- and under- voltage. when the feedback voltage rises higher than 130% of the target voltage, the ovp comparator output goes high, the circuit latches as the hs-fet turns off, and the ls- fet turns on, acting as a -2a current source. to protect the MP8720 from damage, there is an absolute 3.6v ovp on v out when the system is in v out < 3v mode. once v out reaches this value, it latches off. the ls-fet behaves the same as it does at 130% ovp. when the feedback voltage drops below 75% of v ref , but remains higher than 50% of v ref , the uvp-1 comparator output goes high, and the MP8720 latches if v fb remains in this range for about 30s (latching the hs-fet off and the ls-fet on). the ls-fet remains on until the inductor current reaches zero. during this period, the valley current limit helps control the inductor current. when the feedback voltage drops below 50% of v ref , the uvp-2 comparator output goes high, and the MP8720 latches off directly after the comparator and logic delay (latching the hs- fet off and the ls-fet on). the ls-fet remains on until the inductor current reaches zero. fault latching can be reset by driving en low or cycling the power of vin. under-voltage lockout (uvlo) protection the MP8720 has two under-voltage lockout (uvlo) protections: a 3v v cc uvlo and a 4.2v vin uvlo. the MP8720 starts up only when both v cc and vin exceed their respective uvlo thresholds. the MP8720 shuts down when either v cc is lower than the uvlo falling threshold voltage (typically 2.8v) or vin is lower than the 3.8v vin falling threshold. both uvlo protections are non-latch off. if an application requires a higher uvlo, use en to adjust the input voltage uvlo by using two external resistors (see figure 9). figure 9: adjustable uvlo thermal shutdown thermal shutdown is employed in the MP8720. the junction temperature of the ic is monitored internally. if the junction temperature exceeds the threshold value (typically 150c), the converter shuts off. this is a non-latch protection. there is a hysteresis of about 25c. once the junction temperature drops to about 125c, a new soft start is initiated.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 17 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. r application information setting the output voltage with no external ramp the MP8720 does not need ramp compensation for applications where poscap or ceramic capacitors are set as output capacitors (when vin is over 6v), so the external compensation is not needed. the output voltage is then set by feedback resistors r1 and r2 (see figure 10). figure 10: simplified circuit without external ramp first, choose a value for r2. r2 should be chosen reasonably. a small value for r2 leads to considerable quiescent current loss, but an r2 value that is too large makes fb noise- sensitive. it is recommended to choose a value within 5 - 50k ? for r2. use a comparatively larger value for r2 when v out is low; use a smaller value for r2 when v out is high. considering the output ripple, r1 is determined with equation (3): 2 1 r v v v r ref ref out ? ? ? (3) c4 acts as a feed-forward capacitor to improve the transient and can be set in the range of 0 - 1000pf. a larger value for c4 leads to better transient, but it is more noise sensitive. reserve room for a noise filter resistor (r9) (see figure 11). setting the output voltage with external compensation if the system is not stable enough or there is too much jitter when a ceramic capacitor is used on the output (i.e.: with a ceramic c out and vin is 5v or lower), an external voltage ramp should be added to fb through resistor r4 and capacitor c4. since there is already an internal ramp added in the system, a 1m ? (r4), 220pf (c4) ramp should suffice. figure 11: simplified circuit with external ramp besides the r1 and r2 divider, the output voltage is influenced by r4 (see figure 12). r2 should be chosen reasonably. a small value for r2 leads to considerable quiescent current loss, but a value for r2 that is too large makes fb noise sensitive. it is recommended to choose a value within 5 - 50k ? for r2. use a comparatively larger value for r2 when v out is low; use a smaller value for r2 when v out is high. the value of r1 then is determined with equation (4): 2 1 4 2 1 r r r v v v r ref out ref ? ? ? ? (4) to get a pole for better noise immunity, set r9 with equation (5): 9 4sw 1 r 2c2f ? ?? ? (5) set r9 in the range of 100 ? to 1k ? to reduce its influence on the ramp. selecting the input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply ac current to the step-down converter while maintaining the dc input voltage. for the best performance, use ceramic capacitors placed as close to vin as possible. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. the capacitors must have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated with equation (6): out out cin out in in vv ii (1 ) vv ?? ?? (6)
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 18 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the worst-case condition occurs at vin = 2v out , shown in equation (7): out cin i i 2 ? (7) for simplification, choose an input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose an input capacitor that meets the specification. the input voltage ripple can be estimated with equation (8): out out out in sw in in in iv v v(1) fc v v ?? ? ?? ? (8) the worst-case condition occurs at vin = 2v out , shown in equation (9): out in sw in i 1 v 4f c ??? ? (9) selecting the output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated using equation (10): out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc ?? ?? ? ? ??? (10) when using ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance, which mainly causes the output voltage ripple. for simplification, the output voltage ripple can be estimated with equation (11): out out out 2 sw out in vv v(1) 8f lc v ?? ?? ??? (11) the output voltage ripple caused by the esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4. when using poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr dominates the output ripple. the output ripple can be approximated with equation (12): out out out esr sw in vv v(1)r fl v ?? ?? ? ? (12) the maximum output capacitor limitation should be considered in the design application. the MP8720 has a soft-start time period around 1.6ms. if the output capacitor value is too high, the output voltage cannot reach the design value during the soft-start time, causing it to fail to regulate. the maximum output capacitor value (c o_max ) can be limited approximately with equation (13): o_max lim_avg out ss out c(i i)t/v ? ?? (13) where i lim_avg is the average start-up current during the soft-start period (which can be equivalent to the current limit), and t ss is the soft-start time. selecting the inductor an inductor is necessary for supplying constant current to the output load while being driven by the switched input voltage. a larger-value inductor results in less ripple current, resulting in a lower output ripple voltage, but also has a larger physical footprint, a higher series resistance, and a lower saturation current. a good rule for determining the inductance value is to design the peak-to-peak ripple current in the inductor to be in the range of 30% to 50% of the maximum output current, and the peak inductor current below the maximum switch current limit. the inductance value can be calculated with equation (14): out out sw l in vv l(1) fi v ??? ?? (14) where ? i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current (including a short-current), so i sat is recommended to be >13a.
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 19 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pcb layout guidelines efficient pcb layout is critical for stable operation of the ic. a 4-layer layout is strongly recommended to achieve better thermal performance. for best results, refer to figure 12 and follow the guidelines below. 1. place the high-current paths (gnd, vin, and sw) very close to the device with short, direct, and wide traces. a thick pgnd trace under the ic should be top priority. 2. place the input capacitors as close to vin and gnd as possible on the same layer as the ic. 3. place the decoupling capacitor as close to vcc and gnd as possible. 4. keep the switching node (sw) short and away from the feedback network. 5. place the external feedback resistors next to fb. 6. ensure that there is no via on the fb trace. 7. keep the bst voltage path (bst, c3, and sw) as short as possible. 8. keep the vin and gnd pads connected with a large copper plane to achieve better thermal performance. 9. add several vias with 10mil drill/18mil copper width close to the vin and gnd pads to help thermal dissipation. figure 12: recommended pcb layout
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 20 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. design example table 4 shows the application for different output parameter settings when ceramic capacitors are applied. there is a resistor from an external 3.3v supply to 3v3 acting as a ripple noise filter of the 3.3v power supply. it is recommended to have a resistor value from 0 - 5.1 ? depending on the noise level. a size 0402 resistor is sufficient if the 3.3v voltage rises up with ss > 100s. otherwise, a larger resistor (e.g.: 0603/0805) is needed. for applications where vin is 5v or lower, it is recommended to apply the sch shown in figure 14 with a proper external ramp. the MP8720 also supports non-ddr applications with very compact external components (see figure 15). some design examples are provided below when ceramic capacitors are applied: table 4: design example for 700khz f sw v out (v) cout (f) l ( h) r mode ( ? ) c4 (pf) r1 (k ? ) r2 (k ? ) r4 (k ? ) 1.0v 22 x3 0.68 0 220 13.3 20 ns 1.2 22 x3 0.68 0 220 20 20 ns 5 220 f poscap 1.5 float 220 100 13.7 ns 5 22 x6 1.5 float 220 100 10 274
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 21 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits application for 5v output figure 13: 5v output application 1.0v output application figure 14: 1.0v output application
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm MP8720 rev. 1.01 www.monolithicpower.com 22 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits (continued) 5.0v output application with forced ccm figure 15: 5v output application with forced ccm
MP8720 ? 26v, 10a, synchronous buck co nverter with adjustable clm notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP8720 rev. 1.01 www.monolithicpower.com 23 8/1/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-16 (3mmx3mm)

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